The present invention is generally directed to high-speed Ethernet local area networks (LANS) and, more specifically, to a full-duplex transceiver for use in a gigabit Ethernet network.
The rapid proliferation of local area network (LANs) in the corporate environment and the increased demand for time-sensitive delivery of messages and data between users has spurred development of high-speed (gigabit) Ethernet LANs. The 100BASE-TX Ethernet LANs using category-5 (CAT-5) copper wire and the 1000BASE-T Ethernet LANs capable of one gigabit per second (1 Gbps) data rates over CAT-5 data grade wire require new techniques for the transfer of high-speed symbols.
The transfer of high-speed symbols over an Ethernet LAN requires full-duplex gigabit (Gbps) Ethernet transceivers which transmit and receive data over category-5 copper wire at the 1 Gbps data rate. This full-duplex data transfer occurs over four twisted pairs at 125 mega-symbols (125 Mbaud) per second per pair, which is the same as a transfer rate of 500 mega-symbols (Mbaud) per second in each direction.
In an exemplary system, data is transmitted using a five-level pulse amplitude modulation (PAM-5) technique. In PAM-5, data is represented by five voltage levels, designated as an alphabet symbol {A} represented by data bits with the symbol alphabet having values of xe2x88x922, xe2x88x921, 0, 1, 2 volts, for example. The actual voltage levels may differ from these five levels. At each clock cycle, a single one-dimensional (1D) symbol is transmitted on each wire. The four 1D symbols traveling in one direction on each of the conductor pairs at a particular sample time k are considered to be a single four-dimensional (4D) symbol. In addition, extra channel symbols represent Ethernet control characters. Therefore, five level PAM (PAM-5) with either a parity check code or trellis coding is often utilized in Gigabit Ethernet transmission.
At 125 Mbaud, each 4D symbol needs to transmit at least eight bits. Therefore, 256 different 4D symbols plus those required for control characters are required. By transmitting a 4D PAM-5 symbol alphabet, there are 54=625 possible symbols. This number of symbols allows for 100% redundancy in the data as well as for several control codes. Symbol alphabets having more than five symbols yield even greater redundancy.
Another technique for transferring data at high rates is known as non-return to zero (NRZ) signaling. In NRZ, the symbol alphabet {A} has values of xe2x88x921 and +1 volts. A Logical 1 is transmitted as a positive voltage, while a Logical 0 is transmitted as a negative voltage. At 125 mega-symbols per second, the pulse width of each NRZ symbol (the positive or negative voltage) is 8 nano-seconds.
Another modulation method for high speed symbol transfer is known as multi-level transmit-3 (MLT-3) which uses three voltage levels for the transfer of data. This American National Standard Information (ANSI) approved modulation technique is used for the To transfer of data over a 100BASE-TX network using unshielded twisted pairs.
In MLT-3 transmission, a Logic 1 is transmitted as either a xe2x88x921 or a +1 voltage while a Logic 0 is transmitted as a 0 voltage. Thus, the transmission of two consecutive Logic 1s does not require an MLT-3 system to pass data through zero. The transmission of an MLT-3 logical sequence (1, 0, 1) results in transmission of the symbols (+1, 0, xe2x88x921) or (xe2x88x921, 0, +1), depending on the symbols transmitted prior to this sequence. If the symbol transmitted immediately prior to the sequence is a +1, then the symbols (+1, 0, xe2x88x921) are transmitted. If the symbol transmitted before this sequence is a xe2x88x921, then the symbols (xe2x88x921, 0, +1) are transmitted. If the symbol transmitted immediately before this sequence is a 0, then the first symbol of the sequence transmitted will be a +1 if the previous Logic 1 is transmitted as a xe2x88x921 and will be a xe2x88x921 if the previous Logic 1 is transmitted at +1.
The signal-to-noise ratio (SNR) required to achieve a particular bit error rate is higher for MLT-3 signaling than for two level systems. The advantage of the MLT-3 system, however, is that the energy spectrum of the emitted radiation from the MLT-3 system is concentrated at lower frequencies and therefore more easily meets Federal Communications Commission (FCC) radiation emission standards for transmission over twisted pair cables.
Other modulation schemes for multi-symbol coding can also be utilized, including quadrature amplitude modulation (QAM). In QAM schemes, for example, the symbols are arranged on two-dimensional (real and imaginary) symbol constellations (instead of the one-dimension constellations of the PAM-5 or-MLT-3 symbol alphabets.)
These multi-level symbol representations were not needed prior to the development of higher speed computer networks, since data could be transferred between computers at sufficient speeds and accuracy as binary data. However, the higher gigabit per second Ethernet data rate and other communications schemes requires transmitters and receivers capable of transmitting and receiving data over multiple twisted copper pair using larger symbol alphabets (i.e., 3 or more symbols). There is also a need for transceiver (transmitter/receiver) systems that operate at high symbol rates while maintaining low bit error rates (BERs).
As in other communications systems, the transmission cable (or channel) connecting the transmitter and receiver distorts the shape of the transmitted symbol stream. Each symbol transmitted is diffused in the transmission process so that it is commingled with symbols being transmitted at later transmission times. This effect is known as xe2x80x9cintersymbol interferencexe2x80x9d (ISI) and is a result of the dispersive nature of the communication cable. The transmitted waveform is further changed by the cable transmission characteristics, noise which is added over time, and interfacing devices such as transformers, for instance.
When the high-speed signal is received at the transceiver, it is further modified by the physical and operating characteristics of the receiving transceiver. For instance, the impedance that may be seen by the transceiver front-end not only includes the impedance of the cable and the transformer that couples the cable to the transceiver front-end, but also the impedance of on-board traces and input/output structures. Input/output structures include electrostatic discharge protectors, input/output cells, and the like, that may reside on an integrated circuit before the transceiver front-end components.
Therefore, there is a need in the art for improving the performance of full-duplex transceivers for operation at gigabit per second data rates across local area networks. There is a further need in the art for improving the performance of full-duplex transceiver front-ends to compensate for operational changes due to cable and circuit characteristics as well as the lengths of connecting cable. In particular, there is a need for improved transceiver front-ends which accommodate changes due to manufacturing processes and environmental changes across time. More particularly, there is a need in the art for a high performance full-duplex transceiver front-end which incorporates a system for improving performance by cancelling echos and correcting for signal offsets, as well as adjusting performance due to direct current and data dependent drifts and off-sets.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in a high speed Ethernet local area network (LAN), a transceiver comprising: 1) front-end analog signal processing circuitry comprising: a) a line driver capable of receiving an outgoing analog signal from a data source and transmitting the outgoing analog signal to an external cable via a transformer coupling the transceiver to the external cable; b) a DC offset correction circuit capable of receiving an incoming analog signal from the transformer and reducing a DC component in the incoming analog signal; c) an echo canceller capable of receiving the incoming analog signal and reducing in the incoming analog signal an echo component of the outgoing analog signal to thereby produce a reduced-echo incoming analog signal; d) an automatic gain control (AGC) circuit capable of receiving the reduced-echo incoming analog signal and amplifying the reduced-echo incoming analog signal by an adjustable gain factor to thereby produce an amplified incoming analog signal; and e) an adaptive analog equalization filter capable of receiving the amplified incoming analog signal and amplifying a first high frequency component of the amplified incoming analog signal to thereby produce an analog filtered incoming signal; 2) an analog-to-digital converter (ADC) capable of converting the analog filter incoming signal to a first incoming digital signal; and 3) digital signal processing circuitry comprising a digital finite impulse response (FIR) filter capable of receiving the first incoming digital signal and amplifying a second high frequency component of the first incoming digital signal to thereby produce a digital filtered incoming signal.
The present invention provides a new architecture for receiving encoded data streams which have been sent over a cable. A typical application for this receiver is for gigabit 1000 Base-T. The present invention implements a line driver, an adaptive echo canceller, an adaptive gain control stage, an adaptive equalizer for providing a high frequency boost to the incoming signal, an adaptive DC offset correction system, and an analog-digital converter. The echo canceller adapts to the effective impedance of the cable and the transformer. The amount of equalization adapts to the length of the attached cable. The DC offset correction system adapts to correct for the process and manufacturing related offsets accumulated in the front-end. The gain control stage adapts the gain of the front-end to maximize the SNR of the analog-digital converter. The present invention provides the capability for high-performance signal processing for error-free transmission and reception over extended lengths of cable and manufacturing variations. This architecture can be used for a 10 Base-T, 100 Base-TX, and 1000 Base-T transceivers.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.